1. Field of the Invention
This invention relates generally to the manufacturing and distribution of application specific standard product (ASSP) integrated circuits (ICs) including, but not limited to, the manufacturing and distribution of field programmable gate arrays (FPGA).
2. Discussion of the Background
IC fabrication often concludes with the steps of testing, packaging, marking, and dry packing of the IC. Typically, an IC device is tested briefly while still on the wafer. ICs failing this test are discarded. ICs passing the test are packaged (i.e., mounted in plastic or ceramic carriers that protect the IC.) Packaged ICs are then marked (e.g., with product tracking information and other appropriate markings). Packaged ICs that have been marked are then subjected to further tests to determine full functionality and performance. ICs failing these tests are discarded.
Often the fully tested and marked ICs are then dry packed. That is, the ICs are processed to remove residual moisture, usually through baking, and hermetically sealed, typically in vacuum sealed anti-static envelopes.
Conventional ASSP ICs are pre-programmed at the factory to perform a specific function. They have fixed capabilities and are homogenous.
In contradistinction thereto, an FPGA is a programmable IC logic device that includes a matrix of configurable logic blocks (CLBS) embedded in a programmable routing mesh. Thus, an FPGA can be considered a programmable ASSP device and can be programmed after manufacturing. (The device is referred to as an FPGA because the array of CLBs contained on the device can be configured and interconnected in the “field” by the user (as opposed to the manufacturer) by means of special hardware and software.) The combined programming of the CLBs and routing network define the function of the device.
Each CLB can provide one or more of the functions provided by an AND gate, OR gate, flip-flop, latch, inverter, NOR gate, exclusive OR gate, as well as combinations of these functions to form more complex functions. The particular function performed by any one CLB is determined by control signals that are applied thereto from a corresponding control logic circuit. The control logic circuit is formed integrally with, and is part of, the integrated circuit on which the CLB is formed. If desired, control information can be stored and/or generated outside of this integrated circuit and transmitted to the CLB. The actual set of control bits provided to each CLB on the IC depends upon the functions that the CLB and, more globally, the IC are to perform.
Each CLB typically has a plurality of input and output pins, and a set of programmable interconnect points (PIPs) for each input and output pin. The general interconnect structure of the FPGA includes a plurality of interconnect segments and a plurality of PIPs, wherein each interconnect segment is connected to one or more other interconnect segments by programming an associated PIP. An FPGA also includes an access PIP that either connects an interconnect segment to an input pin or an output pin of the CLB.
Because the PIPs in the FPGA are programmable, any given output pin of a CLB is connectable to any given input pin of any other desired CLB. Thus, a specific FPGA configuration having a desired function is created by selected generation of control signals to configure the specific function of each CLB in an FPGA, together with selected generation of control signals to configure the various PIPs that interconnect the CLBs within the FPGA. The configuration data may be read from memory (e.g., an external programmable read-only memory (PROM)) or written into the FPGA by an external device. U.S. Pat. No. 6,020,633 to Erickson and U.S. Pat. No. 6,044,025 to Lawman describe the relationship between the PROM and the FPGA and are incorporated herein by reference.